The invention relates to formation of charge coupled devices and, more particularly, the invention relates to fabrication of two-phase charge coupled devices.
Owing to the cost competitive nature of charge coupled device (CCD) manufacture, it is desirable to provide a high yield, low cost process. Accordingly, two-phase CCDs, having the advantage over three-phase CCDs in manufacturability, speed and resolution, are being manufactured.
One conventional structure of a two-phase CCD is shown in FIG. 1. FIG. 1 depicts a cross-sectional view of a portion of a semiconductor device assembly 20 for a two-phase CCD coupled to signal sources 23 and 24. Signal source 23 and signal source 24 are phase one and two, respectively, and are coupled to gates 21 and 22 with lines 18 and 19, respectively.
Conventionally, semiconductor device assembly 20 is formed on a p-type single crystalline Silicon substrate 10. A n-type implant is used to form buried channel layer (bccd) 11 in substrate 10. Next, a dielectric layer 14 is grown or deposited, after which a conductive layer 16 is deposited over dielectric layer 14. Layers 14 and 16 are etched to form spaced-apart device stacks. After forming gate stacks 21, n-minus wells 13 are formed by implanting a p-type material. Accordingly, bccd 11 comprises n regions 12 and n-minus wells 13 in an alternating sequence. Next, a dielectric layer 15 is formed, conventionally by thermial oxidation whereby a portion of layer 21 is consumed. Next, conductive layer 17 is deposited, and gates 22 are formed. Unfortunately, in the process of removing selected portions of conductive layer 16, remnants, known in the semiconductor industry as xe2x80x9cstringersxe2x80x9d or xe2x80x9csliversxe2x80x9d, are sometimes left behind. These remnants can cause gates 21 to be electrically shorted to one another. Because respective gates 21 are to be electrically separate from one another for a two-phase CCD of the configuration shown in FIG. 1, and because shorting due to stringers or slivers is not typically repairable after forming gates 22, CCD yield is adversely affected.
To address this problem, an alternative structure and process for fabrication of a two-phase CCD is described with reference to FIG. 2. FIG. 2 depicts a cross-sectional view of a portion of a semiconductor device assembly 30 for a two-phase CCD. In the alternative structure, gates 21 are connected to one another and to signal source 23 by lines 18A, and gates 22 are connected to one another and to signal source 24 by lines 19A, as illustratively shown in FIG. 2. Accordingly, shorting together of gates 21 from layer 16 remnant formation is not at issue in device assembly 30.
Marks, not shown, may be made on a semiconductor wafer for registration between the wafer and lithographic equipment, such as a stepper or a step and scan. However, this approach is often dependent on metrological limitations and may require having machine associations with respect to a particular piece of lithographic equipment, and this limits fabrication throughput when the associated piece of lithographic equipment is not readily available. Accordingly, if gates 21 are misaligned, yield is reduced possibly owing to charge trapping or malformation of the device, the CCD may operate in a less than optimal manner.
Therefore, a need exists in the art for a more robust process for forming this alternative structure for a two-phase CCD.
The present invention provides a process for forming a portion of a semiconductor device on a substrate. More particularly, a buried channel layer is formed on the substrate, and a sacrificial layer is deposited over the buried channel layer and patterned to provide spaced-apart rows. A mask is formed extending part way between the rows, and wells are formed in the buried channel layer between the rows using facing sides of the rows and the mask. The mask is removed, and gate stacks between the rows are formed prior to removing the rows. Another mask extending part way between the gate stacks is formed, and other wells are formed in the buried channel layer between the gate stacks using facing sides of the gate stacks and the other mask prior to removing the other mask. Other gate stacks are formed between the existing gate stacks.
Accordingly, it should be appreciated that an aspect of the present invention provides for topological alignment or xe2x80x9cself-alignedxe2x80x9d formation of wells in a buried channel layer. Because these wells are formed in a self-aligned manner, there is less chance for misalignment.